(Update: read the 2/28/11 The New York Times story "Remapping Computer Circuitry to Avert Impending Bottlenecks" for more on this subject)
“What will future computer systems look like?” asks HP Labs distinguished technologist Parthasarathy Ranganathan in a cover story for Computer magazine, the flagship publication of the IEEE Computer Society.
In his article [PDF], Ranganathan suggests computer science is at what he calls an ‘inflection point,’ one that will provoke a radical rethink of traditional computer system design.
This new generation of systems will likely be built around nanostores, argues Ranganathan. Nanostores are non-volatile memory chips that also act as processors – and they promise to dramatically change the speed and volume at which computer systems can work.
Colleagues of Ranganathan in HP’s Intelligent Infrastructure Lab are already developing such memory chips, having in the last several years made significant advances in memristor-based technology. Memristors, a circuit building block with origins dating to the 1970s, are resistors with memory and represent the fourth basic circuit element in electrical engineering. Because they can both store information and act as processors, they have the potential to be the building blocks from which nanostores can be built.
It won’t be too long, HP researchers believe, before computer engineers like Ranganthan will be able to use such memristor-based nanostores in their new system designs.
A new direction for the server market
HP sees its memristor research as key to maintaining the company’s lead in the global server market, says Marc Hamilton, VP of high performance computing for HP’s Industry Standard Servers and Software group.
While the company continued to dominate the competition in 2010 with an industry-leading 31.4% share of worldwide revenue (source: Gartner estimate), Hamilton believes that changes in customer demand will challenge even the most successful players in today’s market.
He notes, for example, that many organizations currently relying on x86 industry standard servers are starting to want ‘hyperscale’ or high performance computing (HPC) systems. These are already being used to run cloud services, in large-scale online social, retail and financial operations and in systems attached to vast arrays of sensors distributed around the world.
Those uses are only going to increase, believes Hamilton. “Consumer goods companies are now using the hyperscale computational fluid dynamics to design their packaging,” he explains. “And you’re starting to see high performance computers move out of the research lab and into clinical use for genome sequencing. In fact, almost every large company today is starting to use high performance computing technology.”
But even newer GPGPU-based systems, like one HP built recently for Tokyo Tech, are constrained by the fundamentals of traditional computing architecture. “If you just use a traditional programming model,” says Hamilton, “they put a tremendous burden on the network and storage interface. People are starting to look at latency-hiding algorithms just to use these systems effectively.”
From the ground up: memristors and rethinking the computer
Hamilton and HP colleagues like Ranganathan argue that, to compete in the coming age of exascale computing, technology companies need to reconsider the fundamental assumptions behind traditional computer architecture. And they believe they’ve found the means to do that with the memristor.
HP Labs recently announced a plan to begin manufacturing memristor-based solid state memory chips, an innovation its researchers predict will then be followed by chips able to both store and do computations in one place.
“The potential here is to transform computing through shifting the balance of compute, storage and networking,” Ranganathan explains.
When stacked together, memristors would, in effect, turn into nanostores that both hold information and do computation on that information. They could also be packed together into ‘microblades.’
“Potentially,” says Ranganathan, “that could let you shrink a whole rack of storage onto a single blade. And then you could shrink a whole data center into a couple of racks of memristor-based nanostores.”
A familiar model – for once
There are plenty of thorny technical issues to be resolved before that can happen, of course. A major question is how lightning-fast memory/processing units would work in a data network, a challenge that HP Labs research is already addressing.
Crucially, though, the fundamental concept of using nanostores and microblades is a familiar one, says ISS’s Hamilton. “It’s similar to what’s being used in big web data centers already,” he explains. “Only a system like Hadoop, which Google uses, is entirely software based. This works in much the same way, only much faster.”
That’s unusual. Typically, new compute models require people to think about software differently – and that slows the model’s adoption. “The computer world has been struggling for the last five years to use the multi-core x86 processor,” notes Hamilton. “Now they are adapting to the use of GPGPU technology. But if you look at both the nanostore in a web environment and the microblade in a dataflow model – neither requires you to rearchitect how you have been doing things. That provides for a very interesting capability to accelerate performance without causing massive change to the software.”
The generation after next
HP’s next-generation servers won’t feature memristors – which aren’t due to appear in the first flash-type memory chips for several years.
But memristor-enhanced servers are currently on the HP road map, says Hamilton.
“Right now we’re doing a lot of conceptual design and looking at how this all fits into our overall architecture,” he explains. “And what we’re seeing is that this new generation of servers is going to enable us to massively extend our successful Converged Infrastructure strategy by enabling a new kind of holistic control of storage, compute and networking.”