AMD's HT Assist on Intel processors?

[#1]

Do Intel processors have a similar feature to AMD’s “HT Assist”?

A customer recently asked me that question after studying AMD's Direct-Connect Architecture. The short answer is “No, but it wouldn't really benefit current Xeon processors."

Here's the long answer: 

AMD's HT Assist feature is a way to reduce latency and increase bandwidth for data flowing between processors in a multi-processor server.

HT Assist sets up a directory in the processor cache that lists what memory chunks are cached in other processors. This lets the processor know for sure which other processor should have the data it wants, rather than having to ask all the processors if they have it.  AMD also calls this a "probe filter" (because it limits how much probing a processor does to other processor's caches). It's also called a "source snooped cache" algorithm.  John Fruehe calls it "the rifle shot instead of the shotgun blast" cache snooping.

The biggest benefit from HT Assist comes in situations where there are a lot of processors, and when processors don't have direct links to all of them. (When you don't have enough direct links, then a probe of a distant processor's cache might require a few "hops", where intermediary processors must relay the request and response.)

 
At first glance, the AMD Opteron 6100 (Magny-Cours) might not look like a candidate for HT Assist.  Each processor as 4 HyperTransport (HT) links available, so a 4-processor system could be build such that each CPU has a direct link to the others:

The reason this link-up won't work is because the Opteron 6100 processor is actually two different dies (chips) inside a single package. It's called an MCM (Multi-Chip Module).  This means the processor has more cores (up to 12), but also means the connection between the two dies consumes one of those inter-processor links.  So, the HT Assist feature on a 4-socket Opteron server yields big benefits.  There's a downside: Some of the L3 cache gets consumed by this memory directory.

Neither Intel's Xeon 5500/5600 series processors, nor their 7500 series processors have an equivalent feature, but for slightly different reasons.

The Xeon 5500 and 5600 (Nehalem-EP and Westmere-EP), designed for 2-socket servers, don't need it.  There are enough inter-processor links (QPI links in Intel parlance) to go around.  Actually, the HT Assist feature is turned off in 2-socket Opteron 6100-based servers for the same reason: it's not necessary (and HP's tests show that  it can actually hurt in that config.)

Since the Xeon 7500 (Nehalem-EX) is a single die, and each has 4 QPI links, there's enough to direct-connect everything. There's no HT Assist-like feature, but as we've just seen, it's not needed.   (Xeon 7500's do use a related snooping technique to track memory chunks that might be in the I/O hub.)   This kind of feature would would assist in Xeon 7500-based servers with more than 4 sockets, though, which is where node controllers come into play.

Here's a detailed description of HT Assist.  To see some Opteron 6100-based servers, check out the ProLiant BL465c G7 and BL685c G7.

[#2]

There's a good explanation in this ProLiant DL980 G7 whitepaper on how the node controller in an 8-processor Xeon 7500 server acts as the "HT Assist"-like cache directory:

http://h20195.www2.hp.com/V2/GetPDF.aspx/4AA3-0643ENW.pdf

[#3]

Intel has said that they will add a feature called Directory Assisted Snoopy (DAS) in their Westmere-EX processors, expected in mid-2011.  This cache-directory feature is similar to HT Assist, although its primary benefit would be for node-less 8-socket servers.