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Harnessing Horsepower: Cores, Capacity, and Code

Last week at IDF, two Intel technologists spoke about different fixes to the problem of compute capacity outpacing the typical server's ability to handle it.
For the past 5 years, x86 CPU makers have boosted performance by adding more cores within the processor.  That's enabled servers with ever-increasing CPU horsepower.   RK Hiremane (speaking on "I/O Innovations for the Enterprise Cloud") says that that I/O subsystems haven't kept pace with this processor capacity, moving the bottleneck for most applications from the CPU to the network and storage subsystems.

He gives the example of virtualized workloads.  Quad-core processors can support the compute demands for a bunch of virtual machines.  However, the typical server I/O subsystem (based on 1Gb Ethernet and SAS hard drives) gets overburdened by the I/O demand of all those virtual machines.  He predicts an immindent evolution (or revolution) in server I/O to fix this problem.

Among other things, he suggests solid-state drives (SSDs) and 10 gigabit Ethernet will be elements of that (r)evolution.  So will new virtualization techniques for network devices.   (BTW, some of the changes he predicts are already being adopted on ProLiant server blades, like embedded 10GbE controllers with "carvable" Flex-10 NICs.   Others, like solid-state drives, are now being widely adopted by many server makers.)

Hold on, said Anwar Ghuloum.  The revolution that's needed is actually in programming, not hardware.   There are still processor bottlenecks holding back performance; they stem from not making the shift in software to parallelism that x86 multi-core requires.

He cites five challenges to mastering parallel programming for x86 multi-core:
* Learning Curve (programmer skill sets)
* Readability (ability for one programmer to read & maintain other programmer's parallel code)
* Correctness (ability to prove a parallel algorithm generates the right results)
* Scalability (ability to scale beyond 2 and 4 cores to 16+)
* Portability (ability to run code on multiple processor families)

Anwar showed off one upcoming C++ library called Ct from RapidMind (now part of Intel) that's being built to help programmers solve these challenges.  (Intel has a Beta program for this software, if you're interested.)

To me, it's obvious that the "solution" is a mix of both.  Server I/O subsystems must (and are) improving, and ISVs are getting better at porting applications to scale with core count.

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